1. Technical Field
This invention relates to chemical mechanical processes for the planarization of surfaces, and to chemical compositions especially suited thereto. More particularly, this invention relates to compositions for the chemical mechanical planarization of conductive, barrier and dielectric surfaces as typically encountered in the fabrication of integrated circuits, including compositions specifically formulated for chemical mechanical planarization and non-contact chemical planarization of Cu/Ta/TaN.
2. Description of Related Art
Fabrication of integrated circuits (xe2x80x9cICsxe2x80x9d) to improve performance and reduce costs involves complex analysis of materials properties, processing technology and IC design. IC""s consist of multiple layers of conducting, insulating and semiconductor materials, interconnected in various ways by conducting metallic channels and plugs (xe2x80x9cviasxe2x80x9d), including various dopants implanted into various materials for producing the electronic functionality desired of the IC. The near-universal trend in the manufacture of integrated circuits is to increase the density of components fabricated onto a given area of wafer, increase the performance and reliability of the ICs, and to manufacture the ICs at lower cost with less waste and fewer defective products generated by the manufacturing process. These goals lead to more stringent geometric and dimensional requirements in the manufacturing process. In particular, etching precise patterns into a layer is facilitated by the layer having a surface as nearly planar as feasible at the start of the patterning process. For the common case of patterning by means of photolithography, a planar surface permits more precise location and dimensioning for focusing the incident radiation onto the surface to be etched than would be possible with a surface having deviations from planarity. Similar conclusions typically apply for electron beam or other means of etching. That is, deviations from planarity of the surface to be etched reduce the ability of the surface to support precisely positioned and precisely dimensioned etches. In the following description of the present invention we focus on the typical etching, planarization and photolithography processes as practiced in the manufacture of ICs. However, this is by way of illustration and not limitation, as those skilled in the art of etching will appreciate that the techniques of the present invention for producing planar surfaces will have applicability in increasing the precision of etching by means other than photolithography. In addition, the present invention is not limited to the field of IC manufacture and may find applicability in other areas of technology requiring planar surfaces.
Chemical Mechanical Planarization (xe2x80x9cCMPxe2x80x9d) has been successfully integrated into integrated circuit multilayer manufacturing processes to achieve highly planar surfaces as described in text books (for example, xe2x80x9cMicrochip Fabricationxe2x80x9d by Peter Van Zant, 3rd Ed., 1997 and xe2x80x9cChemical Mechanical Planarization of Microelectronic Materialsxe2x80x9d by J. H. Steigerwald, S. P. Murarka and R. J. Gutman, 1997) and generally known in the art. We note that xe2x80x9cCMPxe2x80x9d is also used in the art to denote xe2x80x9cChemical Mechanical Polishingxe2x80x9d as well as xe2x80x9cChemical Mechanical Planarizationxe2x80x9d. We use CMP herein synonymously in either sense without distinction.
A typical CMP process is depicted schematically in FIG. 1. During a CMP process, the wafer, 1, is typically held inside a rotating carrier and pressed onto a rotating pad, 2, under pressure, 6, while an abrasive slurry, 5, (typically containing particles of abrasive such as SiO2, Al2O3, and the like) flows between the wafer and the pad. The slurry, 5, will typically contain reagents for chemically etching the wafer, 1, leading to chemical as well as mechanical removal of material. Thus, in the typical practice of CMP, material removal is effected by a combination of chemical attack and mechanical abrasion.
Typically, the wafer, 1, will be caused to rotate as depicted by 3 in FIG. 1, while the polishing pad will itself rotate (4 in FIG. 1). FIG. 1 depicts the polishing pad and wafer rotating in the same direction (for example, clockwise when viewed from above as in FIG. 1). However, this is merely for purposes of illustration and counter-rotation of wafer and polishing pad is also practiced. In addition to the rotation of the wafer depicted by 3 in FIG. 1, the wafer, 1, may be caused to oscillate in the plane of the surface being polished, substantially perpendicular to the direction of the applied force, 6 (This oscillatory motion is not depicted in FIG. 1).
Recent work has indicated the ability to planarize surfaces by purely chemical means, without the need for a polishing pad or mechanical contact with the surface undergoing planarization (Ser. No. 09/356,487, incorporated herein by reference). As described in the referenced application, appropriate etchant chemicals are applied to a spinning wafer under conditions and in such a fashion as to planarize the wafer surface. The techniques described in Ser. No. 09/356,487 are collectively denoted as xe2x80x9cspin etch planarizationxe2x80x9d or SEP. Chemical compositions presented in the present application may be employed in SEP processes for the planarization of Cu/Ta/TaN surfaces as well as in more conventional CMP.
Increasing the speed and performance of ICs typically calls for increasing the density of components on the wafer and increasing the speed at which the IC performs its desired functions. Increasing component density typically requires decreasing the size of conducting channels and vias (or plugs). It is well known that decreasing the cross-section of a current-carrying conductor increases the electrical resistance of the conductor for the same material. Thus, decreasing component size on ICs increases electrical resistance, degrading performance and perhaps leading to unacceptable heating. This is one reason IC developers have been looking for conducting materials for use in IC fabrication having lower electrical resistance. Present IC technology typically makes use of tungsten (chemical symbol W) and aluminum (Al) as conductors. Both have adequate electrical conductivities in present devices, but future generations of IC devices will preferably make use of yet higher conductivity materials. Copper (Cu) is among the leading candidates.
Increasing the density of IC components on the wafer also increases the capacitance of the circuits. That is, bringing charge-carrying circuit elements closer together increases the capacitive coupling between such circuit elements. Higher capacitance is detrimental to circuit performance, especially for higher frequency operation as would typically be encountered in telecommunication applications and elsewhere. However, capacitive coupling between proximate circuit elements can be reduced by reducing the dielectric constant of the insulator or insulating material separating the coupled circuit elements. Thus, in addition to seeking conductors with higher conductivities, insulators with lower dielectric constant (xe2x80x9clow kxe2x80x9d) are also being sought for use as insulating layers in ICs.
Current multi-layer IC fabrication typically makes use of tungsten (W) CMP processes at each successive circuit level. Typically, blanket films of W, Titanium (Ti) and Titanium Nitride (TiN) are deposited. The films are then typically polished, thereby removing material resulting in (for example) W vias or xe2x80x9cplugsxe2x80x9d which are inlaid, typically in an SiO2 dielectric layer. The W plugs act as electrically conducting paths between the metal lines of adjacent layers of the IC. Typically, the metal lines connected by W vias will consists of alloys of Al and Cu in present ICs. In typical present IC designs, Ti and TiN layers are used as barrier layers (to hinder unwanted diffusive intermixing of components during fabrication) and adhesion layers (to promote good bonding between otherwise poorly bound layers and to avoid delamination). Such barrier and adhesion layers must also be removed during W CMP to reveal the inlaid W plugs. Desirable CMP for such ICs should remove the various layers equally and, thus, planarize in one CMP step. Commercially available W slurries can achieve almost the ideal 1:1 removal rate selectivity between W and Ti/TiN layers. This results in a very flat surface of the device wafers after W CMP. Thus, if other combinations of conductor and insulators are to be used in IC fabrication, adequate chemical reagents for CMP must be employed and adequate planarization processes must be used. Such are among the objects of the present invention.
The use of W vias, Alxe2x80x94Cu lines, and SiO2 dielectric layers, although quite successful in present ICs, has inherent drawbacks that hinder attaining the circuit performance desired in future devices. The Alxe2x80x94Cu alloys and W vias are conductive, but less so than Cu. The SiO2 dielectric layers (although good electrical insulators) have a relatively high dielectric constant, leading to deleterious capacitive effects. (xe2x80x9cHigh kxe2x80x9d typically denotes dielectric constants in the range of approximately 3 to 9.) The combination of relatively high resistivity metals and relatively high dielectric constant insulators reduces circuit speed and reliability, particularly as the device geometry is reduced in future ICs below approximately 0.25 xcexcm, (that is 0.25 microns).
Several candidate low k materials for IC dielectric layers include materials having a high degree of porosity. The open structure of such porous materials includes significant amount of airspace. Therefore, in determining the overall effective dielectric constant of the material, lower k values are achieved. However, conventional CMP of porous materials is complicated by the possibility of abrasive CMP particles becoming entrapped in the porous structure. Subsequent cleaning to remove these entrapped abrasive particles from the IC adds to the processing complexity and to the IC cost. Some embodiments of present invention describe a CMP solution without abrasive particles. Thus, when used in connection with porous dielectric materials, these CMP solutions of the present invention offer the advantage of not requiring post-CMP cleanup for removing entrapped abrasives.
Metallic copper (Cu) has a lower resistivity than W or Alxe2x80x94Cu alloys. Therefore, Cu is becoming a popular choice for the interconnect metal to be used in future generation ICs. It is further envisioned that low k dielectric materials (that is, materials with dielectric constants, k, less than about 3.0) will be used in conjunction with Cu metallization to reduce capacitive effects. However, both of these choices bring accompanying challenges in the fabrication of high performance, low cost, reliable ICs. Low k dielectrics are often mechanically weak relative to conventional dielectrics and tend to delaminate under the stress of CMP, especially if the applied pressure, 6, in FIG. 1 must be rather large in order to achieve adequate material removal rates. An adequate rate of material removal is required in order to achieve planarization in an acceptable period of time. Addressing these challenges, the focus of the present invention is on the use of copper, on barrier layers to avoid harmful diffusion of Cu, and slurry compositions for effective Cu CMP (or non-contact planarization also known as xe2x80x9cspin-etch planarizationxe2x80x9d or xe2x80x9cSEPxe2x80x9d) in the presence of effective barrier and adhesion layers. Typical barrier layers in copper damascene or dual damascene fabrication processes include Ta and TaN.
In order to increase performance and reduce manufacturing costs, it is envisioned that Cu metal will most likely be used in future ICs in fabricating the metallic conducting channels within a layer and in the vias which connect adjacent layers. This will likely be accomplished using a xe2x80x9cdamascenexe2x80x9d or xe2x80x9cdual damascenexe2x80x9d manufacturing approach. Damascene processing typically proceeds by depositing a blanket layer of metal on top of a patterned insulating or dielectric layer, thereby filling channels and vias in the patterned insulating layer. When necessary, the metal deposition is preceded by the deposit of a barrier or adhesion layer between the metal and the dielectric. Since trench and via filling is not typically uniform, the metal is deposited to fill the features and covers the field regions between features as well. This blanket metal overlayer is then typically removed by CMP or etching, revealing the inlaid metal channels and vias with a surface ideally coplanar with the field regions of the surrounding dielectric. The barrier layer on the field region is also typically removed in the planarization step. Dual damascene is a two-step damascene process, typically forming more than one layer of features in the dielectric before barrier layer and metal is deposited.
It is envisioned that the metal of choice for the next generations of ICs will be copper. Therefore, to be concrete in our description, we will describe the practice of the present invention in connection with copper damascene or dual damascene processing including the use of Ta/TaN barrier layers. However, the present invention is not inherently so limited and other embodiments will be obvious to those having ordinary skills in the art.
Copper has the advantage of higher conductivity, but suffers from several complications which heretofore have delayed its adoption in ICs. Among copper""s disadvantages is the fact that it is a very diffusive contaminant. That is, copper diffuses widely and easily through other materials typically used in the fabrication of ICs, seriously degrading electronic performance by doing so. It is among the objects of the present invention to address, eliminate or ameliorate some of these attendant drawbacks in the use of Cu metallization in the fabrication of ICs.
In addition to its high rate of diffusion, reaction products of copper with typical etching reagents have often resulted in non-volatile (or insoluble) reaction products. Thus, etching of Cu with conventional CMP slurries has been difficult. Identification of a group of effective copper etching reagents having volatile or soluble reaction products (while maintaining adequate removal rate and selectivity) is among the objectives of the present invention.
Tantalum (Ta) and Tantalum Nitride (TaN) have been identified as promising barrier layer, or xe2x80x9cliner metalsxe2x80x9d, that will prevent harmful Cu diffusion. Because CMP is presently the most effective and well understood planarization technique, it is the natural method with which to undertake the planarization of Cu, Ta or TaN. Such Cu/Ta/TaN CMP requires slurries with high Cu and Ta/TaN removal rates and close to a 1:1 removal selectivity between Cu and the liner metals. However, Ta and TaN are mechanically hard and they do not react readily with most etching chemicals. For these reasons, CMP slurries having appropriate chemical formulations to obtain 1:1 selectivity between Cu and the liner metals have been difficult to achieve. Hence, at present there is no slurry commercially available for Cu CMP.
Typical experimental Cu slurries are composed of H2O2, various oxidizers, alumina and/or silica abrasive, and other chemical components, typically in acidic (low pH) solutions. (Tytgat et. al. U.S. Pat. Nos. 4,981,553; 5,098,571). These formulations typically give good Cu removal rate, but often achieve very low Ta/TaN removal rates, even when high polishing pressures are employed. Currently there are two common experimental approaches being employed for Cu CMP, both of which suffer from disadvantages. In one approach (Brusic, xe2x80x9cA Cautious Approach to the Removal of Ta in the CMP Polishing of Cu/Ta Structuresxe2x80x9d, 193rd Electrochemical Society Meeting, May 1998) Cu CMP is conducted by using a two-step polishing process to remove Cu and Ta/TaN. The Cu and Ta/TaN layers are removed separately in sequence using two distinct slurries. This two step approach significantly complicates the fabrication processes and increases the cost of the CMP process applied to Cu. A single-step Cu CMP would be preferable, but it would require a slurry with 1:1 selectivity for Cu and Ta/TaN. One possible way to increase the removal rate of Ta/TaN layers is to dramatically increase the polishing downforce. However, a higher polishing downforce is contraindicated since it could damage the underlying low k materials, which are often mechanically weak and subject to delamination. Achieving a slurry with the required near 1:1 selectivity without the application of large polishing downforce is among the objects of the present invention.
Slurry formulations that react chemically with inert liner metals to achieve adequate removal rates and selectivity would be an improvement in Cu CMP. A single-step Cu CMP employing a slurry that provides 1:1 selectivity and high material removal rates at low polishing pressures, is highly desirable. However, a two-step CMP slurry that did not require high polishing pressures, though less desirable than the single-step slurry, would still be an improvement in the present art.
The present invention is described for the specific example of CMP slurries for Cu/Ta/TaN on IC wafers as this specific case is expected to be a primary area of applicability of the present invention. However, the compositions and processes of the present invention are not inherently limited to these particular instances. The present invention could be useful for processing many different types of metallic, dielectric, or organic layers, or mixtures and/or composites thereof, on numerous types of substrate for numerous technical applications, as would be known to those skilled in the art. In addition, etchant formulations that may be used in connection with non-contact CMP (or SEP) are described.
Chemical mechanical planarization of surfaces of copper, tantalum and tantalum nitride is accomplished by means of the chemical formulations of the present invention. The chemical formulations may optionally include abrasive particles and such abrasive particles may be chemically reactive or inert. Contact or non-contact CMP may be performed with the present chemical formulations. Substantially 1:1 removal rate selectivity for Cu and Ta/TaN is achieved. In addition to 1:1 removal rate selectivity, the present invention provides adequate material removal rates without excessive downforce being necessary on (often delicate) low dielectric components. Etchant formulations of the present invention are also applicable for use with spin etch planarization.